A few weeks ago I had the opportunity to visit Blue Pearl Software, one of
the emerging EDA companies in Silicon Valley. Blue Pearl Software was started
six years ago with the goal of doing design analysis at the functional level
and providing designers with control of their design from RTL through
synthesis. Another goal as important as the first was to automatically generate
timing constraints and allow the verification of their correctness.

Ellis Smith, the company CEO told me that both goals have been achieved and
that their products, Analyze RTL and Create are the easiest tools to use in the
industry. The user interface is so intuitive that any designers can be
proficient with the tools from the very beginning. The tools use proprietary
technologies that include RTL analysis, high level symbolic simulation, and
state space exploration.

For example, Ellis continued, one can click on any generated false path and
immediately see the entire path from its origin to its final destination and
validate it. This of course saves significant time in the design process. We
all know that time is money.

Analyze RTL combines both linting and formal verification technology to give
a comprehensive static design checking solution. The tool offers both a
Schematic Viewer and a Clock Domain Crossing Viewer. They consist of three
dockable sub-windows within the main schematic window. The Clock Domain
Crossing Viewer window shows a color coded view of the selected path, while the
Schematic Viewer includes a hierarchical design browser that lets an engineer
easily navigate through the design.

Shakeel Jeeawoody, Director of Product Marketing, told me that Blue Pearl
supports design using multiple clocks. Formal clock domain boundary checking
ensures that data crossing clock domain boundaries is synchronized. The tool
automatically recognizes a number of common synchronization methods like double
register buffering, FIFO based synchronization, and multiplexed control based
synchronization. It also supports custom schemes by allowing the designer to
specify the allowed synchronization cells.

The product also identifies data that is generated and consumed by different
edges of the same clock and checks for the appropriate use of lock-up latches.

During the demo I saw that Blue Pearl allows designers to check that the RTL
description complies with design for testability (DFT) rules. Since the tool
understands the ATPG process, a user can perform scan-path integrity.

In short the Create product analyses the RTL description, identifies clock
domains, extracts both false paths and multi-cycle paths, and generates SDC
timing constraints and assertions.

Those who know me and have read my writings remember that I have said more
than once that demos are engineered to show the best parts of the product, and
thus one cannot make a final judgment from a demo. But I have to say that Blue
Pearl Software\'s approach and technology to shorten the development time is
robust and deserving of investigation. As almost all emerging EDA companies,
Blue Pearl concentrates on engineering investment and thus does not have a
major voice in marketing. I asked Shakeel to give me his elevator speech.

\"Our suite of tools automatically checks HDL descriptions for
compliance with user-selected and user-defined properties, including netlist
checks and advanced property checks for CDC. We generate and manage timing
constraints from RTL by statically identifying complex false and multi-cycle
paths that occur due to complex control logic.

Our visual timing constraints verification provides an internal audit trail
that shows the schematic representation of the false path and explains the
logical conflict at the source of the path. Combined with automatically
generated assertions we believe this provides a method that engineers can trust
and use to save development time and increase reliability.\"

Just like with real pearls, one must look inside the shell to find the gem.

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